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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. AM29LV652D data sheet publication number 24961 revision a amendment +4 issue date october 29, 2004
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preliminary this data sheet states amd?s current technical specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 24961 rev: a amendment/ +4 issue date: october 29, 2004 r efe r to amd? s website (www.a m d.co m ) fo r t h e latest i n fo rm atio n . AM29LV652D 128 megabit (16 m x 8-bit) cmos 3.0 volt-only uniform sector flash memory with versatileio ? control distinctive characteristics two 64 megabit (am29lv065d) in a single 63-ball 11 x 12 mm fbga package (note: features will be described for each internal am29lv065d) two chip enable inputs ? each ce# controls selection of one internal am29lv065d device single power supply operation ? 3.0 to 3.6 volt read, erase, and program operations versatileio ? control ? device generates output voltages and tolerates input voltages on dq i/os as determined by the voltage on v io input high performance ? access times as fast as 90 ns manufactured on 0.23 m process technology cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ultra low power consumption (typical values at 3.0 v, 5 mhz) for the part ? 9 ma typical active read current ? 26 ma typical erase/program current ? 400 na typical standby mode current flexible sector architecture ? two hundred fifty-six 64 kbyte sectors sector protection ? a hardware method to lock a sector to prevent program or erase operations within that sector ? sectors can be locked in-system or via programming equipment ? temporary sector unprotect feature allows code changes in previously locked sectors embedded algorithms ? embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ? embedded program algorithm automatically writes and verifies data at specified addresses compatibility with jedec standards ? except for the added ce2#, the fbga is pinout and software compatible with single-power supply flash ? superior inadvertent write protection minimum 1 million erase cycle guarantee per sector 63-ball fbga package erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation data# polling and toggle bits ? provides a software method of detecting program or erase operation completion unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ready/busy# output (ry/by#) ? provides a hardware method of detecting program or erase cycle completion hardware reset input (reset#) ? hardware method to reset the device for reading array data acc input ? accelerates programming time for higher throughput during system production program and erase performance (v hh not applied to the acc input) ? byte program time: 5 s typical ? sector erase time: 1.6 s typical for each 64 kbyte sector 20-year data retention at 125 c ? reliable operation for the life of the system
2 AM29LV652D october 29, 2004 preliminary general description the AM29LV652D is a 128 mbit, 3.0 volt (3.0 v to 3.6 v) single power supply flash memory device organized as two am29lv065d dice in a single 63-ball fbga package. each am29lv065d is a 64 mbit, 3.0 volt (3.0 v to 3.6 v) single power supply flash memory de- vice organized as 8,388,608 bytes. data appears on dq0-dq7. the device is designed to be programmed in-system with the standard system 3.0 volt v cc sup- ply. a 12.0 volt v pp is not required for program or erase operations. the AM29LV652D is equipped with two ce#s for flexible selection between the two inter- nal 64 mb devices. the device can also be pro- grammed in standard eprom programmers. the AM29LV652D offers access times of 90 and 120 ns and is offered in a 63-ball fbga package. to elimi- nate bus contention the AM29LV652D device contains two separate chip enables (ce# and ce2#). each chip enable (ce# or ce2#) is connected to only one of the two dice in the AM29LV652D package. to the sys- tem, this device is the same as two independent am29lv065d on the same board. the only differ- ence is that they are now packaged together to re- duce board space. each device requires only a single 3.0 volt power supply (3.0 v to 3.6 v) for both read and write func- tions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the command register using standard microprocessor write timing. register con- tents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically preprograms the array (if it is not already pro- grammed) before executing the erase operation. dur- ing erase, the device automatically times the erase pulse widths and verifies proper cell margin. the versatilei/o? (v io ) control allows the host sys- tem to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on v io . this allows the device to operate in a 3 v or 5 v system environment as required. for voltage levels below 3 v, contact an amd representative for more in- formation. the host system can detect whether a program or erase operation is complete by observing ry/by#, by reading the dq7 (data# polling), or dq6 (toggle) sta- tus bits . after a program or erase cycle is completed, the device is ready to read array data or accept an- other command. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# terminates any operation in progress and resets the internal state machine to reading array data. reset# may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the flash memory device. the device offers a standby mode as a power-saving feature. once the system places the device into the standby mode power consumption is greatly reduced. the accelerated program (acc) feature allows the system to program the device at a much faster rate. when acc is pulled high to v hh , the device enters the unlock bypass mode, enabling the user to reduce the time needed to do the program operation. this feature is intended to increase factory throughput during sys- tem production, but may also be used in the field if de- sired. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunnelling. the data is programmed using hot electron injection.
october 29, 2004 AM29LV652D 3 preliminary table of contents distinctive characteristi cs . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 2 product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . . 9 table 1. AM29LV652D device bus operations ................................9 versatileio ? (v io ) control ....................................................... 9 requirements for reading array data ..................................... 9 writing commands/command sequences ............................ 10 accelerated program operation .......................................... 10 autoselect functions ........................................................... 10 standby mode ........................................................................ 10 automatic sleep mode ........................................................... 10 reset#: hardware reset pin ............................................... 10 output disable mode .............................................................. 11 table 2. sector address table for ce# ..........................................11 table 3. sector address table for ce2# ........................................15 autoselect mode ..................................................................... 19 table 4. AM29LV652D autoselect codes, (high voltage method) 19 sector group protection and unprotection ............................. 20 table 5. sector group protection/unprotection address table .....20 temporary sector group unprotect ....................................... 21 figure 1. temporary sector group unprotect operation................ 21 figure 2. in-system sector group protect/unprotect algorithms ... 22 hardware data protection ...................................................... 23 low vcc write inhibit ......................................................... 23 write pulse ?glitch? protection ............................................ 23 logical inhibit ...................................................................... 23 power-up write inhibit ......................................................... 23 common flash memory interface (cfi) . . . . . . . 23 table 6. cfi query identification string .......................................... 23 system interface string................................................................... 24 table 8. device geometry definition .............................................. 24 table 9. primary vendor-specific extended query ........................ 25 command definitions . . . . . . . . . . . . . . . . . . . . . 25 reading array data ................................................................ 25 reset command ..................................................................... 26 autoselect command sequence ............................................ 26 byte program command sequence ....................................... 26 unlock bypass command sequence .................................. 26 figure 3. program operation .......................................................... 27 chip erase command sequence ........................................... 27 sector erase command sequence ........................................ 28 erase suspend/erase resume commands ........................... 28 figure 4. erase operation............................................................... 29 table 10. AM29LV652D command definitions ............................. 30 write operation status . . . . . . . . . . . . . . . . . . . . 31 dq7: data# polling ................................................................. 31 figure 5. data# polling algorithm .................................................. 31 ry/by#: ready/busy# ............................................................ 32 dq6: toggle bit i .................................................................... 32 figure 6. toggle bit algorithm........................................................ 32 dq2: toggle bit ii ................................................................... 33 reading toggle bits dq6/dq2 ............................................... 33 dq5: exceeded timing limits ................................................ 33 dq3: sector erase timer ....................................................... 33 table 11. write operation status ................................................... 34 absolute maximum ratings . . . . . . . . . . . . . . . . 35 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 7. maximum negative overshoot waveform ..................... 35 figure 8. maximum positive overshoot waveform....................... 35 dc characteristics (for two am29lv065 devices) 36 figure 9. i cc1 current vs. time (showing active and automatic sleep currents) ............................................................. 37 figure 10. typical i cc1 vs. frequency ............................................ 37 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. test setup.................................................................... 38 table 12. test specifications ......................................................... 38 figure 12. input waveforms and measurement levels ................. 38 key to switching waveforms. . . . . . . . . . . . . . . . 38 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 read-only operations ........................................................... 39 figure 13. read operation timings ............................................... 39 hardware reset (reset#) .................................................... 40 figure 14. reset timings ............................................................... 40 erase and program operations .............................................. 41 figure 15. program operation timings.......................................... 42 figure 16. accelerated program timing diagram.......................... 42 figure 17. chip/sector erase operation timings .......................... 43 figure 18. data# polling timings (during embedded algorithms). 44 figure 19. toggle bit timings (during embedded algorithms)...... 45 figure 20. dq2 vs. dq6................................................................. 45 temporary sector unprotect .................................................. 46 figure 21. temporary sector group unprotect timing diagram ... 46 figure 22. sector group protect and unprotect timing diagram .. 47 figure 23. alternate ce# controlled write (erase/program) operation timings .............................................. 49 erase and programming performance . . . . . . . 50 latchup characteristics . . . . . . . . . . . . . . . . . . . . 50 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 51 fsa063?63-ball fine-pitch ball grid array (fbga) 11 x 12 mm package .................................................................................. 51 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 52
4 AM29LV652D october 29, 2004 preliminary product selector guide note: see ?ac characteristics? on page 39 for full specifications. part number AM29LV652D speed option regulated voltage range: v cc = 3.0?3.6 v 90r 12r max access time (ns) 90 120 ce# access time (ns) 90 120 oe# access time (ns) 35 50
october 29, 2004 AM29LV652D 5 preliminary block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# acc ce# oe# stb stb dq0 ? dq7 sector switches ry/by# reset# data latch y-gating cell matrix address latch v io input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register stb stb dq0 ? dq7 sector switches ry/by# data latch y-gating cell matrix address latch v io a0?a22 a0?a22 a0?a22 ce#2
6 AM29LV652D october 29, 2004 preliminary connection diagram special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. c2 d2 c3 d3 e2 e3 f2 f3 g2 g3 h2 h3 j2 j3 k2 a3 a4 a2 a1 a0 ce# oe# v ss a7 a18 a6 a5 dq0 nc ce2# dq1 ry/by# acc nc nc dq2 dq3 v io a21 we# reset# a22 nc dq5 nc v cc dq4 a9 a8 a11 a12 a19 a10 dq6 dq7 a14 a13 a15 a16 a17 nc a20 v ss c4 d4 e4 a1 b1 a2 nc* nc* nc* f4 g4 h4 j4 k4 c5 d5 e5 f5 g5 h5 j5 k5 c6 d6 e6 f6 g6 h6 j6 k6 c7 d7 e7 nc* nc* nc* nc* a7 b7 a8 b8 f7 g7 h7 j7 k7 nc* nc* nc* nc* l7 m7 l8 m8 k3 l1 l2 m1 nc* nc* nc* nc* m2 * balls are shorted together via the substrate but not connected to the die. 63-ball fbga top view, balls facing down
october 29, 2004 AM29LV652D 7 preliminary pin description a0?a22 = 23 addresses inputs dq0?dq7 = 8 data inputs/outputs ce# = chip enable input ce2# = chip enable input for second die oe# = output enable input we# = write enable input acc = acceleration input reset# = hardware reset pin input ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally logic symbol 23 8 dq0?dq7 a0?a22 ce# ce2# oe# acc ry/by# we# v io reset#
8 AM29LV652D october 29, 2004 preliminary ordering information standard products amd standard products are available in several packages and ope rating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM29LV652D u 90r ma i temperature range i = industrial (?40 c to +85 c) e = extended (?55 c to +125 c) f = industrial (-40 o c to +85 o c) with pb-free package k = extended (-55 o c to +125 o c) with pb-free package package type ma = 63-ball fine-pitch ball grid array (fbga) 0.80 mm pitch, 11 x 12 mm package (fsa063) speed option see product selector guide and valid combinations sector architecture u = uniform sector device device number/description AM29LV652D 128 megabit (2 x 8 m x 8-bit) cmos uniform sector flash memory with versatileio ? control 3.0 volt-only read, program, and erase valid combinations for fbga packages speed/ v io range order number package marking AM29LV652Du90r maf, mai l652du90r f, i 90 ns, v io = 3.0 v ? 5.0 v AM29LV652Du12r mai, mae maf, mak l652du12r i, e, f, k 120 ns, v io = 3.0 v ? 5.0 v
october 29, 2004 AM29LV652D 9 preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. AM29LV652D device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 8.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. ce# can be replaced with ce2# when referring to the second die in the package. ce# and ce2# must not both be driven at the same time. 2. addresses are a22:a0. sector addresses are a22:a16. 3. d in or d out as required by command sequence, data polli ng, or sector protect algorithm (see figure 2 ). 4. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 5. all sectors are unprotected when shipped from the factory. versatileio ? (v io ) control the versatileio (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data in- puts to the same voltage level that is asserted on v io . this allows the device to operate in a 3 v or 5 v sys- tem environment as required. for voltage levels below 3 v, contact an amd representative for more informa- tion. for example, a v i/o of 4.5?5.0 volts allows for i/o at the 5 volt level, driving and receiving signals to and from other 5 v devices on the same data bus. requirements for reading array data to read array data from the outputs, the system must drive ce# or ce2# and oe# to v il . ce# or ce2# is the power control and selects the device. oe# is the out- put control and gates array data to the outputs. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains operation ce# (note 1) oe# we# reset# acc addresses (note 2) dq0?dq7 read l l h h x a in d out write (program/erase) l h l h x a in (note 3) accelerated program l h l h v hh a in (note 3) standby v cc 0.3 v x x v cc 0.3 v h xhigh-z output disable l h h h x xhigh-z reset x x x l x xhigh-z sector group protect (note 4) l h l v id x sa, a6 = l, a1 = h, a0 = l (note 3) sector group unprotect (note 4) lhlv id x sa, a6 = h, a1 = h, a0 = l (note 3) temporary sector group unprotect xxxv id x a in (note 3)
10 AM29LV652D october 29, 2004 preliminary enabled for read access until the command register contents are altered. see ?versatileio ? (v io ) control? for more information. refer to the ac ?read-only operations? on page 39 table for timing specifications and to figure 13, on page 39 for the timing diagram. i cc1 in the dc charac- teristics table represents the active current specifica- tion for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# (or ce2#) to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a byte, instead of four. the ?byte program command sequence? on page 26 section contains details on programming data to the device using both standard and unlock bypass command se- quences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2, on page 11 indicates the address space that each sector occupies. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. if the system asserts v hh on acc, the device automat- ically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage to reduce the time required for program operations. the syst em would use a two-cy- cle program command sequence as required by the unlock bypass mode. removing v hh from acc re- turns the device to normal operation. note that acc must not be at v hh for operations other than acceler- ated programming, or device damage may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? on page 19 and ?autoselect command sequence? on page 26 sections for more information. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce#, ce2#, and reset# are all held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce#, ce2#, and reset# are held at v ih , but not within v cc 0.3 v, the device is in the standby mode, but the standby current is greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics (for two am29lv065 de- vices) table represents the standby current specifica- tion. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, ce2#, we#, and oe# control signals. stan- dard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics (for two am29lv065 de- vices) table represents the automatic sleep mode cur- rent specification. reset#: hardware reset pin reset# provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all out- puts, and ignores all read/write commands for the du- ration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il, but not within v ss 0.3 v, the standby current is greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory,
october 29, 2004 AM29LV652D 11 preliminary enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted duri ng a program or erase op- eration, ry/by# remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the sys- tem can read data t rh after reset# returns to v ih . refer to the ?ac characteristics? on page 39 tables for reset# parameters and to figure 14, on page 40 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. table 2. sector address table for ce# (sheet 1 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal) sa0 0000000 000000?00 ffff sa1 0000001 010000?01 ffff sa2 0000010 020000?02 ffff sa3 0000011 030000?03 ffff sa4 0000100 040000?04 ffff sa5 0000101 050000?05 ffff sa6 0000110 060000?06 ffff sa7 0000111 070000?07 ffff sa8 0001000 080000?08 ffff sa9 0001001 090000?09 ffff sa10 0001010 0a0000?0affff sa11 0001011 0b0000?0bffff sa12 0001100 0c0000?0cffff sa13 0001101 0d0000?0dffff sa14 0001110 0e0000?0effff sa15 0001111 0f0000?0f ffff sa16 0010000 100000?10 ffff sa17 0010001 110000?11ffff sa18 0010010 120000?12 ffff sa19 0010011 130000?13 ffff sa20 0010100 140000?14 ffff sa21 0010101 150000?15 ffff sa22 0010110 160000?16 ffff sa23 0010111 170000?17 ffff sa24 0011000 180000?18 ffff sa25 0011001 190000?19 ffff sa26 0011010 1a0000?1affff
12 AM29LV652D october 29, 2004 preliminary sa27 0011011 1b0000?1bffff sa28 0011100 1c0000?1cffff sa29 0011101 1d0000?1dffff sa30 0011110 1e0000?1effff sa31 0011111 1f0000?1f ffff sa32 0100000 200000?20 ffff sa33 0100001 210000?21 ffff sa34 0100010 220000?22 ffff sa35 0100011 230000?23 ffff sa36 0100100 240000?24 ffff sa37 0100101 250000?25 ffff sa38 0100110 260000?26 ffff sa39 0100111 270000?27 ffff sa40 0101000 280000?28 ffff sa41 0101001 290000?29 ffff sa42 0101010 2a0000?2affff sa43 0101011 2b0000?2bffff sa44 0101100 2c0000?2cffff sa45 0101101 2d0000?2dffff sa46 0101110 2e0000?2effff sa47 0101111 2f0000?2f ffff sa48 0110000 300000?30 ffff sa49 0110001 310000?31 ffff sa50 0110010 320000?32 ffff sa51 0110011 330000?33 ffff sa52 0110100 340000?34 ffff sa53 0110101 350000?35 ffff sa54 0110110 360000?36 ffff sa55 0110111 370000?37 ffff sa56 0111000 380000?38 ffff sa57 0111001 390000?39 ffff sa58 0111010 3a0000?3affff sa59 0111011 3b0000?3bffff sa60 0111100 3c0000?3cffff sa61 0111101 3d0000?3dffff table 2. sector address table for ce# (sheet 2 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
october 29, 2004 AM29LV652D 13 preliminary sa62 0111110 3e0000?3effff sa63 0111111 3f0000?3f ffff sa64 1000000 400000?40 ffff sa65 1000001 410000?41 ffff sa66 1000010 420000?42 ffff sa67 1000011 430000?43 ffff sa68 1000100 440000?44 ffff sa69 1000101 450000?45 ffff sa70 1000110 460000?46 ffff sa71 1000111 470000?47 ffff sa72 1001000 480000?48 ffff sa73 1001001 490000?49 ffff sa74 1001010 4a0000?4affff sa75 1001011 4b0000?4bffff sa76 1001100 4c0000?4cffff sa77 1001101 4d0000?4dffff sa78 1001110 4e0000?4effff sa79 1001111 4f0000?4f ffff sa80 1010000 500000?50 ffff sa81 1010001 510000?51 ffff sa82 1010010 520000?52 ffff sa83 1010011 530000?53 ffff sa84 1010100 540000?54 ffff sa85 1010101 550000?55 ffff sa86 1010110 560000?56 ffff sa87 1010111 570000?57 ffff sa88 1011000 580000?58 ffff sa89 1011001 590000?59 ffff sa90 1011010 5a0000?5affff sa91 1011011 5b0000?5bffff sa92 1011100 5c0000?5cffff sa93 1011101 5d0000?5dffff sa94 1011110 5e0000?5effff sa95 1011111 5f0000?5f ffff sa96 1100000 600000?60 ffff table 2. sector address table for ce# (sheet 3 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
14 AM29LV652D october 29, 2004 preliminary note: all sectors are 64 kbytes in size. sa97 1100001 610000?61 ffff sa98 1100010 620000?62 ffff sa99 1100011 630000?63 ffff sa100 1100100 640000?64 ffff sa101 1100101 650000?65 ffff sa102 1100110 660000?66 ffff sa103 1100111 670000?67 ffff sa104 1101000 680000?68 ffff sa105 1101001 690000?69 ffff sa106 1101010 6a0000?6affff sa107 1101011 6b0000?6bffff sa108 1101100 6c0000?6cffff sa109 1101101 6d0000?6dffff sa110 1101110 6e0000?6effff sa111 1101111 6f0000?6f ffff sa112 1110000 700000?70 ffff sa113 1110001 710000?71 ffff sa114 1110010 720000?72 ffff sa115 1110011 730000?73 ffff sa116 1110100 740000?74 ffff sa117 1110101 750000?75 ffff sa118 1110110 760000?76 ffff sa119 1110111 770000?77 ffff sa120 1111000 780000?78 ffff sa121 1111001 790000?79 ffff sa122 1111010 7a0000?7affff sa123 1111011 7b0000?7bffff sa124 1111100 7c0000?7cffff sa125 1111101 7d0000?7dffff sa126 1111110 7e0000?7effff sa127 1111111 7f0000?7f ffff table 2. sector address table for ce# (sheet 4 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
october 29, 2004 AM29LV652D 15 preliminary table 3. sector address table for ce2# (sheet 1 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal) sa0 0000000 000000?00 ffff sa1 0000001 010000?01 ffff sa2 0000010 020000?02 ffff sa3 0000011 030000?03 ffff sa4 0000100 040000?04 ffff sa5 0000101 050000?05 ffff sa6 0000110 060000?06 ffff sa7 0000111 070000?07 ffff sa8 0001000 080000?08 ffff sa9 0001001 090000?09 ffff sa10 0001010 0a0000?0affff sa11 0001011 0b0000?0bffff sa12 0001100 0c0000?0cffff sa13 0001101 0d0000?0dffff sa14 0001110 0e0000?0effff sa15 0001111 0f0000?0f ffff sa16 0010000 100000?10 ffff sa17 0010001 110000?11ffff sa18 0010010 120000?12 ffff sa19 0010011 130000?13 ffff sa20 0010100 140000?14 ffff sa21 0010101 150000?15 ffff sa22 0010110 160000?16 ffff sa23 0010111 170000?17 ffff sa24 0011000 180000?18 ffff sa25 0011001 190000?19 ffff sa26 0011010 1a0000?1affff sa27 0011011 1b0000?1bffff sa28 0011100 1c0000?1cffff sa29 0011101 1d0000?1dffff sa30 0011110 1e0000?1effff sa31 0011111 1f0000?1f ffff sa32 0100000 200000?20 ffff sa33 0100001 210000?21 ffff
16 AM29LV652D october 29, 2004 preliminary sa34 0100010 220000?22 ffff sa35 0100011 230000?23 ffff sa36 0100100 240000?24 ffff sa37 0100101 250000?25 ffff sa38 0100110 260000?26 ffff sa39 0100111 270000?27 ffff sa40 0101000 280000?28 ffff sa41 0101001 290000?29 ffff sa42 0101010 2a0000?2affff sa43 0101011 2b0000?2bffff sa44 0101100 2c0000?2cffff sa45 0101101 2d0000?2dffff sa46 0101110 2e0000?2effff sa47 0101111 2f0000?2f ffff sa48 0110000 300000?30 ffff sa49 0110001 310000?31 ffff sa50 0110010 320000?32 ffff sa51 0110011 330000?33 ffff sa52 0110100 340000?34 ffff sa53 0110101 350000?35 ffff sa54 0110110 360000?36 ffff sa55 0110111 370000?37 ffff sa56 0111000 380000?38 ffff sa57 0111001 390000?39 ffff sa58 0111010 3a0000?3affff sa59 0111011 3b0000?3bffff sa60 0111100 3c0000?3cffff sa61 0111101 3d0000?3dffff sa62 0111110 3e0000?3effff sa63 0111111 3f0000?3f ffff sa64 1000000 400000?40 ffff sa65 1000001 410000?41 ffff sa66 1000010 420000?42 ffff sa67 1000011 430000?43 ffff sa68 1000100 440000?44 ffff table 3. sector address table for ce2# (sheet 2 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
october 29, 2004 AM29LV652D 17 preliminary sa69 1000101 450000?45 ffff sa70 1000110 460000?46 ffff sa71 1000111 470000?47 ffff sa72 1001000 480000?48 ffff sa73 1001001 490000?49 ffff sa74 1001010 4a0000?4affff sa75 1001011 4b0000?4bffff sa76 1001100 4c0000?4cffff sa77 1001101 4d0000?4dffff sa78 1001110 4e0000?4effff sa79 1001111 4f0000?4f ffff sa80 1010000 500000?50 ffff sa81 1010001 510000?51 ffff sa82 1010010 520000?52 ffff sa83 1010011 530000?53 ffff sa84 1010100 540000?54 ffff sa85 1010101 550000?55 ffff sa86 1010110 560000?56 ffff sa87 1010111 570000?57 ffff sa88 1011000 580000?58 ffff sa89 1011001 590000?59 ffff sa90 1011010 5a0000?5affff sa91 1011011 5b0000?5bffff sa92 1011100 5c0000?5cffff sa93 1011101 5d0000?5dffff sa94 1011110 5e0000?5effff sa95 1011111 5f0000?5f ffff sa96 1100000 600000?60 ffff sa97 1100001 610000?61 ffff sa98 1100010 620000?62 ffff sa99 1100011 630000?63 ffff sa100 1100100 640000?64 ffff sa101 1100101 650000?65 ffff sa102 1100110 660000?66 ffff sa103 1100111 670000?67 ffff table 3. sector address table for ce2# (sheet 3 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
18 AM29LV652D october 29, 2004 preliminary note: all sectors are 64 kbytes in size. sa104 1101000 680000?68 ffff sa105 1101001 690000?69 ffff sa106 1101010 6a0000?6affff sa107 1101011 6b0000?6bffff sa108 1101100 6c0000?6cffff sa109 1101101 6d0000?6dffff sa110 1101110 6e0000?6effff sa111 1101111 6f0000?6f ffff sa112 1110000 700000?70 ffff sa113 1110001 710000?71 ffff sa114 1110010 720000?72 ffff sa115 1110011 730000?73 ffff sa116 1110100 740000?74 ffff sa117 1110101 750000?75 ffff sa118 1110110 760000?76 ffff sa119 1110111 770000?77 ffff sa120 1111000 780000?78 ffff sa121 1111001 790000?79 ffff sa122 1111010 7a0000?7affff sa123 1111011 7b0000?7bffff sa124 1111100 7c0000?7cffff sa125 1111101 7d0000?7dffff sa126 1111110 7e0000?7effff sa127 1111111 7f0000?7f ffff table 3. sector address table for ce2# (sheet 4 of 4) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
october 29, 2004 AM29LV652D 19 preliminary autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sect or protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (8.5 v to 12.5 v) on address a9. addresses a6, a1, and a0 must be as shown in table 4, on page 19 . in addition, when verifying sector protection, the sector address must appear on the ap- propriate highest order address bits (see table 2, on page 11 and table 3, on page 15 ). ta ble 4 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the pro- gramming equipment may then read the correspond- ing identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 10, on page 30 . this method does not require v id . refer to the ?au- toselect command sequence? on page 26 section for more information. table 4. AM29LV652D autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. notes: 1. ce# can be replaced with ce2# when referring to the second die in the package. 2. the device id?s used for the am29lv652 are the same as the am29lv065, because the am29lv652 uses two am29lv065 dice and appears to the system as two am29lv065 devices. description ce# oe# we# a22 to a16 a15 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id : amd l l h x x v id xlxll 01h device id: AM29LV652D l l h x x v id xlxlh 93h sector protection verification llhsaxv id xlxhl 01h (protected), 00h (unprotected)
20 AM29LV652D october 29, 2004 preliminary sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see table 5 ). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/unprotection can be implemented via two methods. the primary method requires v id on reset# only, and can be implemented either in-system or via pro- gramming equipment. figure 2, on page 22 shows the algorithms and figure 22, on page 47 shows the tim- ing diagram. this method uses standard microproces- sor bus cycle timing. for sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. some earlier 3.0 volt-only amd flash devices used a sector protection/unprotection method intended only for programming equipment, and required v id on ad- dress a9 and oe#. if this earlier method is required for the intended application, contact amd for further de- tails. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and protecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the ?autoselect mode? on page 19 section for details. table 5. sector group protection/unprotection address table note: all sector groups are 256 kbytes in size. sector group a22?a18 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 sa64?sa67 10000 sa68?sa71 10001 sa72?sa75 10010 sa76?sa79 10011 sa80?sa83 10100 sa84?sa87 10101 sa88?sa91 10110 sa92?sa95 10111 sa96?sa99 11000 sa100?sa103 11001 sa104?sa107 11010 sa108?sa111 11011 sa112?sa115 11100 sa116?sa119 11101 sa120?sa123 11110 sa124?sa127 11111
october 29, 2004 AM29LV652D 21 preliminary temporary sector group unprotect ( note: in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see table 5, on page 20 )). this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting reset# to v id (8.5 v ? 12.5 v). during this mode, formerly protected sector groups can be pro- grammed or erased by selecting the sector group ad- dresses. once v id is removed from reset#, all the previously protected sector groups are protected again. figure 1, on page 21 shows the algo- rithm, and figure 21, on page 46 shows the timing dia- grams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected. 2. all previously protected sector groups are protected once again.
22 AM29LV652D october 29, 2004 preliminary figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6 = 0, a1 = 1, a0 = 0 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address twith a6 = 0, a1 = 1, a0 = 0 read from sector group address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6 = 1, a1 = 1, a0 = 0 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6 = 1, a1 = 1, a0 = 0 read from sector group address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
october 29, 2004 AM29LV652D 23 preliminary hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10, on page 30 for command definitions). in addition, the fol- lowing hardware data protection measures prevent ac- cidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce#, ce2#, or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih , ce2# = v ih or we# = v ih . to initiate a write cycle, ce# (or ce2#), and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = ce2# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. the am29lv652 is a two die solution which appears as two 64 mbit am29lv065 devices in the system. this allows the same cfi information to be used be- cause the system ?sees? two 64 mbit devices, not a single 128 mbit device. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, any time the device is ready to read array data (addresses are don?t care). the system can read cfi information at the ad- dresses given in table 6, on page 23 to table 9, on page 25 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 6, on page 23 to table 9, on page 25 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/prod- ucts/nvd/overview/cfi.html. alternatively, contact an amd representative for copies of these documents. table 6. cfi query identification string addresses (x8) data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set 15h 16h 40h 00h address for primary extended table 17h 18h 00h 00h alternate oem command set (00h = none exists) 19h 1ah 00h 00h address for alternate oem extended table (00h = none exists)
24 AM29LV652D october 29, 2004 preliminary table 7. system interface string table 8. device geometry definition addresses (x8) data description 1bh 27h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 36h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 00h v pp min. voltage (00h = no v pp input present) 1eh 00h v pp max. voltage (00h = no v pp input present) 1fh 04h typical timeout per single byte write 2 n s 20h 00h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0ah typical timeout per individual block erase 2 n ms 22h 00h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 05h max. timeout for byte write 2 n times typical 24h 00h max. timeout for buffer write 2 n times typical 25h 04h max. timeout per individual block erase 2 n times typical 26h 00h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (x8) data description 27h 17h device size = 2 n byte 28h 29h 00h 00h flash device interface description (refer to cfi publication 100) 2ah 2bh 00h 00h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 01h number of erase block regions within device 2dh 2eh 2fh 30h 7fh 00h 00h 01h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 00h 00h 00h 00h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 00h 00h 00h 00h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 00h 00h 00h 00h erase block region 4 information (refer to cfi publication 100)
october 29, 2004 AM29LV652D 25 preliminary table 9. primary vendor-specific extended query command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 10, on page 30 defines the valid register command sequences. writing incorrect ad- dress and data values or writing them in the im- proper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce# (or ce2#), whichever happens later. all data is latched on the rising edge of we# or ce# (or ce2#), whichever happens first. refer to ?ac characteristics? on page 39 for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume com- mands? on page 28 for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. addresses (x8) data description 40h 41h 42h 50h 52h 49h query-unique ascii string ?pri? 43h 31h major version number, ascii 44h 31h minor version number, ascii 45h 01h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 02h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 04h sector protect 0 = not supported, x = number of sectors in per group 48h 01h sector temporary unprotect 00 = not supported, 01 = supported 49h 04h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 00h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 000h burst mode type 00 = not supported, 01 = supported 4ch 00h page mode type 00 = not supported 4dh b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 00h top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device
26 AM29LV652D october 29, 2004 preliminary see the next section, ?reset command? , for more in- formation. see also ?versatileio ? (v io ) control? on page 9 for more information. the read-only operations table provides the read parameters, and figure 13, on page 39 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 10, on page 30 shows the address and data re- quirements. this method is an alternative to that shown in table 4, on page 19 , which is intended for prom programmers and requires v id on address a9. the autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while t he device is actively pro- gramming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: a read cycle at address xx00h returns the manu- facturer code. a read cycle at address xx01h returns the device code. a read cycle to an address containing a sector group address (sa), and the address 02h on a7?a0 returns 01h if the sector group is protected, or 00h if it is unprotected. (refer to table 5, on page 20 for valid sector addresses). the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). byte program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 10, on page 30 shows the address and data requirements for the byte pro- gram command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. refer to the ?write operation status? on page 31 section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device returns to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read shows that the data is still ?0.? only eras e operations c an convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing
october 29, 2004 AM29LV652D 27 preliminary two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. table 10, on page 30 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. the device offers accelerated program operations through acc. when the system asserts v hh on acc, the device automatically enters the unlock bypass mode. the system may then write the two-cycle un- lock bypass program command sequence. the device uses the higher voltage on acc to accelerate the op- eration. note that acc must not be at v hh for opera- tions other than accelerated programming, or device damage may result. figure 3, on page 27 illustrates the algorithm for the program operation. refer to the ?erase and program operations? on page 41 table in the ac characteris- tics section for parameters, and figure 15, on page 42 for timing diagrams. figure 3. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 10, on page 30 shows the address and data requirements for the chip erase command sequence. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 10, on page 30 for program command sequence.
28 AM29LV652D october 29, 2004 preliminary when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to ?write operation status? on page 31 for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. figure 4, on page 29 illustrates the algorithm for the erase operation. refer to the ?erase and program op- erations? on page 41 tables in the ac characteristics section for parameters, and figure 17, on page 43 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 10, on page 30 shows the address and data requirements for the sec- tor erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see ?dq3: sector erase timer? on page 33 .). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progr ess, the system can read data from the non-erasing sector. the system can de- termine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing sector. refer to ?write operation status? on page 31 for infor- mation on these status bits. once the sector erase operation begins, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device returns to read- ing array data, to ensure data integrity. figure 4, on page 29 illustrates the algorithm for the erase operation. refer to the ?erase and program op- erations? on page 41 tables in the ac characteristics section for parameters, and figure 17, on page 43 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation is suspended, the device en- ters the erase-suspend-read mode. the system can read data from or program data to any sector not se- lected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status infor- mation on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is ac- tively erasing or is erase-suspended. refer to ?write operation status? on page 31 for information on these status bits.
october 29, 2004 AM29LV652D 29 preliminary after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to ?write operation status? on page 31 for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the ?autoselect mode? on page 19 and ?autoselect com- mand sequence? on page 26 sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writ- ing this command. further writes of the resume com- mand are ignored. another erase suspend command can be written after the chip resumes erasing. figure 4. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 10, on page 30 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
30 AM29LV652D october 29, 2004 preliminary command definitions table 10. AM29LV652D command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# (or ce2#) pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# (or ce2#) pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a22?a16 uniquely select any sector. notes: 1. see table 1, on page 9 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. unless otherwise noted, address bits a22?a12 are don?t cares. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high (while the device is providing status information). 7. the fourth cycle of the autoselect command sequence is a read cycle. see the autoselect command sequence section for more information. 8. the data is 00h for an unprotected sector group and 01h for a protected sector group. 9. the unlock bypass command is required prior to the unlock bypass program command. 10. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 11. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 12. the erase resume command is valid only during the erase suspend mode. 13. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 xxx aa xxx 55 xxx 90 x00 01 device id 4 xxx aa xxx 55 xxx 90 x01 93 sector group protect verify (note 8) 4 xxx aa xxx 55 xxx 90 (sa)x02 00/01 program 4xxxaaxxx 55 xxx a0 pa pd unlock bypass 3 xxxaaxxx 55 xxx 20 unlock bypass program (note 9) 2 xxx a0 pa pd unlock bypass reset (note 10) 2 xxx 90 xxx 00 chip erase 6 xxx aa xxx 55 xxx 80 xxx aa xxx 55 xxx 10 sector erase 6 xxx aa xxx 55 xxx 80 xxx aa xxx 55 sa 30 erase suspend (note 11) 1 ba b0 erase resume (note 12) 1 ba 30 cfi query (note 13) 1 xx 98
october 29, 2004 AM29LV652D 31 preliminary write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 11, on page 34 and the following subsections describe the function of thes e bits. dq7 and dq6 each offer a method for determining whether a program or erase oper- ation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or is completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device completes the program or erase operation and dq7 contains valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 appears on succes- sive read cycles. ?write operation status? on page 34 shows the out- puts for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 18, on page 44 in the ac characteristics section shows the data# polling timing diagram. figure 5. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?q0 addr = va read dq7?q0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
32 AM29LV652D october 29, 2004 preliminary ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by#s can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode. table 11, on page 34 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# (or ce2#) to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can us e dq7 (see the subsection on ?dq7: data# polling? on page 31 ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 11, on page 34 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm. fig- ure 19, on page 45 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 20, on page 45 shows the differences between dq2 and dq6 in graphical form. see also the subsection ?dq2: tog- gle bit ii? on page 33 . figure 6. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
october 29, 2004 AM29LV652D 33 preliminary dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# or ce2# to control the read cycles.) but dq2 cannot dis- tinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are se- lected for erasure. thus, both status bits are required for sector and mode information. refer to table 11, on page 34 to compare outputs for dq2 and dq6. figure 6, on page 32 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? ex- plains the algorithm. see also the dq6: toggle bit i subsection. figure 19, on page 45 shows the toggle bit timing diagram. figure 20, on page 45 shows the dif- ferences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6, on page 32 for the following discus- sion. whenever the system initially begins reading tog- gle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typi- cally, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 6, on page 32 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit is exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure began. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also ?sector erase command sequence? on page 28 after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device accepts additional sector erase commands. to ensure the command is accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 11, on page 34 shows the status of dq3 relative to the other status bits.
34 AM29LV652D october 29, 2004 preliminary table 11. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
october 29, 2004 AM29LV652D 35 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +5.5 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . .?0.5 v to +12.5 v all others (note 1) . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, input or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/os is v cc +0.5 v. see figure 7, on page 35 . during voltage transitions, input or i/os may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8, on page 35 . 2. minimum dc input voltage on a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7, on page 35 . maximum dc input voltage on a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . .?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . .?55c to +125c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 v?3.6 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 v?5.0 v operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 7. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 8. maximum positive overshoot waveform
36 AM29LV652D october 29, 2004 preliminary dc characteristics (for two am29lv065 devices) cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. assumes only one am29lv065 die being programmed at the same time. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 400 na. 6. if v io < v cc , maximum v il for ce# (or ce2#) is 0.3 v io . if v io < v cc , minimum v ih for ce# (or ce2#) is 0.3 v io . 7. not 100% tested. 8. ce# can be replaced with ce2# when referring to the second device within the package. 9. specifications in the table are for the am29lv652 i.e. two am29lv065 dice. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 70 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2) ce# (or ce2#) = v il , oe# = v ih 5 mhz 9 16 ma 1 mhz 2 4 i cc2 v cc active write current (notes 2, 3, 4) ce# (or ce2#) = v il , oe# = v ih 26 30 ma i cc3 v cc standby current (note 2) ce#, ce2#, reset# = v cc 0.3 v 0.4 10 a i cc4 v cc reset current (note 2) reset# = v ss 0.3 v 0.4 10 a i cc5 automatic sleep mode (notes 2, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.4 10 a i acc acc accelerated program current (note 4) ce# = v il , oe# = v ih acc 5 10 ma v cc 15 30 ma v il input low voltage (note 6) ?0.5 0.8 v v ih input high voltage (note 6) 0.7 x v cc v cc + 0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 8.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage (note 7) i oh = ?2.0 ma, v cc = v cc min 0.85 v io v v oh2 i oh = ?100 a, v cc = v cc min v io ?0.4 v v lko low v cc lock-out voltage (note 7) 2.3 2.5 v
october 29, 2004 AM29LV652D 37 preliminary dc characteristics zero-power flash note: addresses are switching at 1 mhz figure 9. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 1 2345 frequency in mhz supply current in ma note: t = 25 c figure 10. typical i cc1 vs. frequency 4 6 12 3.0 v 3.6 v
38 AM29LV652D october 29, 2004 preliminary test conditions table 12. test specifications note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms 2.7 k ? c l 6.2 k ? 3.3 v device under te s t note: diodes are in3064 or equivalent figure 11. test setup test condition 90r 12r unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 12. input waveforms and measurement levels waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
october 29, 2004 AM29LV652D 39 preliminary ac characteristics read-only operations notes: 1. all test setups assume v io = v cc . 2. not 100% tested. 3. see figure 11, on page 38 and table 12, on page 38 for test specifications 4. ce# can be replaced with ce2# when referring to the second device within the package. . parameter description test setup (note 1) speed options jedec std. 90r 12r unit t avav t rc read cycle time (note 2) min 90 120 ns t avqv t acc address to output delay ce#, oe# = v il max 90 120 ns t elqv t ce chip enable to output delay oe# = v il max 90 120 ns t glqv t oe output enable to output delay max 35 50 ns t ehqz t df chip enable to output high z (note 2) max 30 30 ns t ghqz t df output enable to output high z (note 2) max 30 30 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 2) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# or ce2# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 13. read operation timings
40 AM29LV652D october 29, 2004 preliminary ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready c e# or ce2#, oe# t rh c e# or ce2#, oe# reset timings during embedded algorithms reset# t rp t rb figure 14. reset timings
october 29, 2004 AM29LV652D 41 preliminary ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? on page 50 section for more information. 3. ce# can be replaced with ce2# when referring to the second device within the package. parameter speed options jedec std. description 90r 12r unit t avav t wc write cycle time (note 1) min 90 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 50 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 50 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 50 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 byte programming operation (note 2) typ 5 s t whwh1 t whwh1 accelerated byte programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.6 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay min 90 ns
42 AM29LV652D october 29, 2004 preliminary ac characteristics oe# we# ce# or ce2# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs xxxh pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n ote: pa = program address, pd = program data, d out is the true data at the program address. figure 15. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 16. accelerated program timing diagram
october 29, 2004 AM29LV652D 43 preliminary ac characteristics oe# ce# or ce2# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555 h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy note: sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status? on page 31 . figure 17. chip/sector erase operation timings
44 AM29LV652D october 29, 2004 preliminary ac characteristics we# ce# or ce2# oe# high z t oe high z dq7 dq0?q6 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 18. data# polling timings (during embedded algorithms)
october 29, 2004 AM29LV652D 45 preliminary ac characteristics oe# ce# or ce2# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid dat a valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 19. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 20. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
46 AM29LV652D october 29, 2004 preliminary ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector group unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih c e# or ce2# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 21. temporary sector group unprotect timing diagram
october 29, 2004 AM29LV652D 47 preliminary ac characteristics sector group protect: 150 ? sector group unprot ect: 15 ms 1 ? reset# sa, a6, a1, a0 data c e# or ce2# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih * for sector group protect, a6 = 0, a1 = 1, a0 = 0. for sector group unprotect, a6 = 1, a1 = 1, a0 = 0. figure 22. sector group protect and unprotect timing diagram
48 AM29LV652D october 29, 2004 preliminary ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. ce# can be replaced with ce2# when referring to the second device within the package. parameter speed options jedec std description 90r 12r unit t avav t wc write cycle time (note 1) min 90 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 50 ns t dveh t ds data setup time min 45 50 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 50 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 byte programming operation (note 2) typ 5 s t whwh1 t whwh1 accelerated byte programming operation (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.6 sec
october 29, 2004 AM29LV652D 49 preliminary ac characteristics t ghel t ws oe# ce# or ce2# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. figure 23. alternate ce# controlled write (erase/program) operation timings
50 AM29LV652D october 29, 2004 preliminary erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 3.0 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10, on page 30 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all connections except v cc . test conditions: v cc = 3.0 v, one connection at a time. input/output capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 1.6 15 sec excludes 00h programming prior to erasure (note 4) chip erase time 205 sec byte program time 5 150 s excludes system level overhead (note 5) accelerated byte program time 4 120 s chip program time (note 3) 42 126 sec description min max input voltage with respect to v ss on all device connections (including a9, oe#, and reset#) except i/os ?1.0 v 12.5 v input voltage with respect to v ss on all i/os ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 1216pf c out output capacitance v out = 0 1216pf c e /c e2 control pin capacitance v in = 0 6 8 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
october 29, 2004 AM29LV652D 51 preliminary physical dimensions fsa063?63-ball fine-pitch ball grid array (fbga) 11 x 12 mm package
52 AM29LV652D october 29, 2004 preliminary revision summary revision a (may 24, 2001) initial release. revision a+1 (july 31, 2001) ac characteristics?alternate ce# controlled erase and program table t whwh1 ?byte programming operation: changed typi- cal value from 11 s to 5 s. t whwh1 ?accelerated byte programming operation: changed typical value from 7 s to 4 s. revision a+2 (august 14, 2001) global removed the speed options for 100 ns with v io = 1.8 v ? 2.9 v and 120 ns with v io = 1.8 v ? 2.9 v. changed the speed option for 120 ns with v io = 3.0 v ? 5.0 v from 120r to 12r. general description and device bus operations added ?for voltage levels below 3 v, contact an amd representative for more information.? to versatilei/o? text. ordering information removed the optional processing from the order number. revision a+3 (january 10, 2002) global clarified description of versatileio (v io ) in the follow- ing sections: distinctive characteristics; general de- scription; versatileio (v io ) control; operating ranges; dc characteristics; cmos compatible. revision a+4 (october 29, 2004 global added spansion cover sheet added reference links to page numbers added colophon ordering information added two package types to temperature range. valid combination for fbga packages added maf and mak to order number. added f and k to package marking.
53 AM29LV652D october 29, 2004 preliminary colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general office use, personal use, and household use, but ar e not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i .e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport c ontrol, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connecti on with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or lo ss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operat- ing conditions. if any products described in this document represent goods or technologies subject to certain restrictions on e xport under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for ex port of those product trademarks copyright ? 2000 -2004 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are r egistered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication ar e for identification purposes only and may be trademarks of their respective companies

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